Wafer guide in wafer cleaning apparatus

ABSTRACT

A wafer guide in a wafer cleaning apparatus comprises of a lower panel portion. The wafer guide also comprises of a plurality of wafer supporting panel portions, the plurality of wafer supporting panel portions being configured to protrude from at least one side of the lower panel portion and support a wafer. The wafer guide also comprises of a plurality of slot portions, the plurality of slot portions being configured to form at upper ends of the plurality of wafer supporting panel portions and hold the wafer by forming contact with at least a portion of a wafer edge area without forming contact with a wafer cell area.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to semiconductor devicemanufacturing equipment and, more particularly, to a wafer cleaningapparatus which removes impurities on the surface of a wafer.

This application claims the benefit of Korean Patent Application No.10-2005-0116945, filed Dec. 2, 2005, in the Korean Intellectual PropertyOffice, the disclosure of which is incorporated herein by reference inits entirety.

2. Description of the Related Art

Semiconductor devices are manufactured using various processes such as,for example, an impurity ion implantation process, a thin filmdeposition process, an etching process, and a chemical mechanicalpolishing (CMP) process. The impurity ion implantation process implants3B or 5B group impurity ions into a semiconductor. The thin filmdeposition process forms one or more layers on a semiconductorsubstrate. The etching process patterns the one or more layers formed onthe semiconductor substrate in a predetermined pattern. The CMP processlevels the wafer surface by polishing the wafer surface after thedeposition of a layer such as an interlayer insulating layer on thewafer.

While the above-mentioned processes may be used to fabricatesemiconductor devices, these processes also generate contaminants. Thesecontaminants may adhere to the surface of the semiconductor wafer duringthe manufacturing of the semiconductor device. There is therefore a needfor a wafer cleaning process to clean the wafer periodically during thesemiconductor manufacturing process.

Generally, during a wafer cleaning process, a wafer to be cleaned isheld in a wafer vessel which is also known as a wafer guide. A waferguide is disclosed in Korean Patent No.10-0512183 and U.S. Pat. No.6,235,147. The wafer guide includes slots for holding the wafer.Furthermore, the wafers held in the slot portions are immersed intochemical bathes for cleaning, and are moved to a drying portion to drythe wafers.

When wafers held in a wafer guide are moved from one spot to another,the movement of the wafer guide may produce vibrations that may damagethe wafers. In order to protect the wafers from vibrations, the wafersmay be inserted deep into slots of the wafer guide. The deep insertionof the wafers in the slots of the wafer guide may increase the stabilityof the held wafers thus protecting the wafers from vibrations.

However, inserting wafers deep into the slots of the wafer guide maycause problems. For example, studies show that as the wafers areinserted deep into the slots, the amount of wafer surface coming incontact with the slots increases. This increase in the contact surfacebetween the wafer and the slot may lead to a greater possibility of thewafer being damaged. The damage to the wafer may occur because ofscratches forming on the wafer surface in contact with the slot.Furthermore, as a cleaning solution flows through the scratches,additional defects may also be formed in the wafer.

The problems due to scratches on a wafer are exacerbated when theintegration density of a semiconductor device is increased.Specifically, when the integration density of semiconductors isincreased, there is a tendency to position cells closer to the edge of awafer so as to increase the number of cells per wafer. Thus, there arenow more cells on a wafer surface that is directly in contact with aslot holding the wafer. This design issue coupled with the problem of anincrease in the contact surface between a slot and a wafer may increasethe number of scratch related defects in semiconductor wafers. Theseproblems may decrease the production yield of the semiconductormanufacturing process.

In a conventional wafer guide, slot portions for holding wafers areformed at positions such that the slot portions may hold the wafer atthe center of a wafer flat zone. Thus, for example, when wafers areloaded in a conventional wafer guide such that the wafer flat zone isoriented towards the bottom, an area that is 4.4 mm from the wafer edgearea may be in contact with the slot portions of the wafer guide. On theother hand, when wafers are loaded in a conventional wafer guide suchthat the wafer flat zone is oriented towards the top, an area that is 6mm from the wafer edge area may be in contact with the slot portions ofthe wafer guide. FIGS. 1 through 3 show exemplary intervals between awafer edge area and a wafer cell area in currently produced wafers.

FIG. 1 illustrates a first wafer in which the distance between a waferedge area 10 and a wafer cell area 12 is 5 mm. FIG. 2 illustrates asecond wafer in which the distance between a wafer edge area 20 and awafer cell area 22 is 4 mm. FIG. 3 illustrates a third wafer in whichthe distance between a wafer edge area 30 and a wafer cell area 32 is3.5 mm.

Under certain conditions, when wafers of FIGS. 1 through 3 are loaded inthe conventional wafer guide, scratches may occur in the wafer cellareas. For example, when the first wafer in which the distance between awafer edge area 10 and a wafer cell area 12 is 5 mm, is loaded such thatthe wafer flat zone is oriented towards the bottom, no scratches occurin the wafer cell area 12. However, when the first wafer is loaded suchthat the wafer flat zone is oriented towards the top, scratches occur inthe wafer cell area 12 because the length of contact between the slotportion and the wafer surface (6 mm) exceeds the distance of 5 mmbetween the wafer edge area 10 and the wafer cell area 12. Furthermore,in the second wafer (in which the distance between the wafer edge area20 and the wafer cell area 22 is 4 mm) and the third wafer (in which thedistance between the wafer edge area 30 and the wafer cell area 32 is3.5 mm,) the length of contact between the slot portion and the wafersurface exceeds the distance between the wafer edge area and the wafercell area, regardless of the direction of loading the wafers (i.e.,regardless of whether the wafer flat zone is oriented towards the bottomor top.) Therefore, it is likely that scratches will occur in the wafercell area leading to defects in the wafer and to a decrease in theproduction yield of the semiconductor manufacturing process.

FIGS. 4A and 4B depict wafer cell areas that include scratches.Referring to FIGS. 4A and 4B, each wafer cell area 42 is separated fromother cell areas by a scribe line 40. Furthermore, each cell area 42includes scratches 44 that are formed because of the contact between aslot portion and the wafer cell area 42.

FIGS. 5A and 5B depict a wafer cell area having defects caused by fluidsflowing along the scratches 44. Specifically, when a wafer withscratches 44 in the wafer cell area (as shown in FIGS. 4A and 4B) isimmersed into a chemical bath, a cleaning solution flows along thescratch tracks. As a result, a defect 46 caused by the movement of fluidalong the scratches 44 occurs. Defect 46 may include, for example, theremoval of a layer such as poly-silicon that functions as a storageelectrode, from the wafer cell area 42. Such a defect caused by themovement of fluids through the wafer cell area may also result in adecrease in the production yield of the semiconductor manufacturingprocess.

The present disclosure is directed towards overcoming one or moreshortcomings of the conventional wafer guide apparatus.

SUMMARY OF THE INVENTION

One aspect of the present disclosure includes a wafer guide in a wafercleaning apparatus. The wafer guide comprises of a lower panel portion.The wafer guide also comprises of a plurality of wafer supporting panelportions, the plurality of wafer supporting panel portions beingconfigured to protrude from at least one side of the lower panel portionand support a wafer. The wafer guide also comprises of a plurality ofslot portions, the plurality of slot portions being configured to format upper ends of the plurality of wafer supporting panel portions andhold the wafer by forming contact with at least a portion of a waferedge area without forming contact with a wafer cell area.

Another aspect of the present disclosure includes a wafer guide in awafer cleaning apparatus. The wafer guide comprises of a lower panelportion. The wafer guide also comprises of a pair of outer wafersupporting panel portions, formed at right and left side edges of thelower panel portion, supporting a wafer. The wafer guide also comprisesof a pair of inner wafer supporting panel portions formed between thepair of outer wafer supporting panel portions and spaced apart from eachother by a distance exceeding a length of a wafer flat zone, supportingthe wafer. The wafer guide also comprises of a plurality of slotportions, formed at upper ends of the pair of outer wafer supportingpanel portions and the pair of inner wafer supporting panel portions,holding the wafer by forming contact with at least a portion of a waferedge area without forming contact with a wafer cell area.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent to those of ordinary skill in the art bydescribing in detail preferred embodiments thereof with reference to theattached drawings in which:

FIGS. 1 through 3 illustrate the distance between a wafer cell area anda wafer edge area in exemplary wafers, respectively;

FIGS. 4A and 4B depict a wafer cell area including scratches;

FIGS. 5A and 5B depict a wafer cell area including defects caused by themovement of fluid along the scratches;

FIG. 6 illustrates a wafer cleaning apparatus including a wafer guideaccording to an exemplary disclosed embodiment;

FIG. 7 is a front view of the wafer guide according to an exemplarydisclosed embodiment;

FIG. 8 is a side view of the wafer guide according to an exemplarydisclosed embodiment;

FIG. 9 is a perspective view of the wafer guide according to anexemplary disclosed embodiment;

FIG. 10 is a partially enlarged view of an outer wafer supporting panelportion of the wafer guide according to an exemplary disclosedembodiment;

FIG. 11 illustrates a state when a wafer is held in the outer wafersupporting panel portion of FIG. 10;

FIG. 12 is a partially enlarged view of an inner wafer supporting panelportion of the wafer guide according to an exemplary disclosedembodiment; and

FIG. 13 illustrates a state when a wafer is held in the inner wafersupporting panel portion of FIG. 12.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described with reference to theaccompanying drawings, in which preferred embodiments of the inventionare shown. However, the invention should not be construed as limited toonly the embodiments set forth herein. Rather, the present invention maybe embodied in many different forms, and the embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art.

Various unit processes such as, for example, an ion implantationprocess, deposition process, and etching process, are performed on awafer during a semiconductor fabrication process. These unit processesalso generate contaminants. These contaminants may include materiallayers such as a photosensitive layer that is not removed properlyduring an etching process, or reaction byproducts such as polymers.Furthermore, these polymers adhere to the surface of a semiconductorwafer and may cause various problems including chip failure. In order toreduce the chances of chip failure due to these contaminants, it isadvisable to clean the wafer during the semiconductor fabricationprocess to remove the contaminants. It is therefore necessary toimplement a wafer cleaning process in addition to the other processesused in the semiconductor fabrication process.

With the increase in density of semiconductor chips, and the consequentincrease in density of cells per unit area of a wafer, the cleaning of awafer surface assumes even greater importance because even a smallamount of contamination may cause defects in the wafer. It is alsoadvisable to implement a wafer cleaning process before and after eachunit process used in the manufacturing of a semiconductor device.

The wafer cleaning process includes two types of cleaning—wet cleaningand dry cleaning. The wet cleaning process uses chemicals and the drytype cleaning uses vapor or plasma.

The wet cleaning process includes cleaning, rinsing, and drying. Thecleaning process includes immersing the wafer in a cleaning solution.Specifically, an acid or alkaline solution may be used to clean thewafer. The type of cleaning solution used may depend on the type ofimpurities to be removed. For example, an acid such as H₂SO₄ may be usedto remove organic impurities whereas a hydrogen fluoride solution may beused to remove a native oxide layer. The concentration, amount, andtemperature of the cleaning solution used may depend on the type ofwafer to be cleaned and the cleaning conditions such as the cleaningapparatus.

After the cleaning process is completed, the cleaned wafer may besubject to a rinsing process. During the rinsing process, the cleaningsolution stuck to the wafer is removed by using liquids such as, forexample, DI (de-ionized) water. Specifically, DI water is sprayed ontothe surface of the wafer to remove the cleaning solution from thesurface of the wafer. In addition, a wafer may be subject to multiplerinse processes. For example, prior to the drying process, a final rinseprocess may involve the use of DI water wherein the temperature of theDI water is maintained in a desired range such as, for example, 23-25°C. Furthermore, the drying process is used to dry the wafer after it iscleaned and rinsed. The drying process may include the use of an IPAdrier to remove the DI water from the wafer surface.

In addition, a wafer may be physically cleaned. Specifically, thephysical cleaning method includes a rinse method and a D-sonic method.In the rinse method, a wafer is cleaned by spraying DI water onto thesurface of a wafer. Furthermore, the wafer is loaded on a spinningapparatus. The spinning apparatus is configured such that the wafer isspun at a high speed as the wafer is rinsed. In the D-sonic method,contaminants are removed by spraying DI water onto the wafer surface andfurther applying D-sonic power onto the wafer surface.

FIG. 6 illustrates a wafer cleaning apparatus 100. Wafer cleaningapparatus 100 includes a first loading unit 102, a first counter 104, analigning unit 106, a separating unit 108, a wafer guide 110, a secondloading unit 112, a water bath 114, chemical baths 116-1 through 116-n,a drying unit 118, a second counter unit 120, and an unloading unit 122.As described above, a wet cleaning process includes cleaning, rinsing,and drying. An exemplary wet cleaning process that uses wafer cleaningapparatus 100 will now be described below.

A cassette C including a plurality of wafers W is placed in the firstloading unit 102. The cassette C is then transferred by a conveyer (notshown), to the first counter 104 which checks the number of the wafersin the cassette C. The cassette C then passes through the aligning unit106. The aligning unit 106 aligns the flat zones of the plurality ofwafers W in one direction. The cassette C then moves to a separatingunit 108. The separating unit 108 separates the wafers W from thecassette C. Specifically, the separating unit 108 includes the waferguide 110. The wafers W are transferred from the cassette C to the waferguide 110 in the separating unit 108. The wafers W in the wafer guide110 are vertically supported by slot portions formed on the upper end ofthe wafer guide 110. Furthermore, the wafers W that are unloaded fromthe cassette C onto the wafer guide 110 are cleaned by the chemicalbaths 116-1 through 116-n before they are reloaded onto the cassette Catthe second loading unit 112. The cassette C, after transferring thewafers W to the wafer guide 108, moves (using the conveyor) to thesecond loading unit 112. The second loading unit 112 loads the cleanwafers onto the cassette C. Until the second loading unit 112 loads theclean wafers onto the cassette C, the cassette C stays in a standby modeat the second loading unit 112.

After being reloaded with the clean wafers by the second loading unit112, the cassette C is transferred by the conveyor to the second counterunit 120. The second counter unit 120 compares the number of wafers W inthe cassette C at this time with the number recorded by the firstcounter unit 104, thereby verifying whether any wafer is missing in thesection between the separating unit 108 and the second loading unit 112.Upon verification of the correct number of wafers W on the cassette C,the cassette C is transferred to the unloading unit 122. The unloadingunit 122 unloads the cleaned wafers from the cassette C.

The chemical baths 116-1 through 116-n clean the wafers W in the waferguide 110. The cleaned wafers are then dried in the drying unit 118. Thecleaning and drying process will now be described in detail.

The section between the separating unit 108 and the second loading unit112 includes a plurality of chemical bathes 116-1 through 116-n. Thesection also includes the ultra pure water bath 114 and the drying unit118 that are positioned inline with the plurality of chemical baths. Theplurality of chemical bathes 116-1 through 116-n include cleaningsolutions having different composition ratios and differentcharacteristics. The wafers W in the wafer guide 110 are selectivelyplaced into the chemical bathes 116-1 through 116-n and the drying unit118 by at least one or more transfer robots R1 through Rn. Furthermore,similar to the chemical baths, the plurality of transfer robots R1through Rn, are positioned in the section between the separating unit108 and the second loading unit 112.

In particular, each wafer W in the wafer guide 110 is placed into thedesired chemical bath (e.g., 116-1) by the transfer robot R (e.g., R1)designated for that particular chemical bath. Upon completion of thecleaning process in the chemical bath, the wafer W may be transferredinto another cleaning bath (e.g., 116-2) by the designated transferrobot R (e.g., R2) for the other cleaning bath. Alternatively, thecleaned wafer W may be transferred directly to the drying unit 118.Ultimately, all the cleaned wafers will be transferred to the dryingunit 118. The number of cleaning baths in which the wafer W is immersedwill depend on the type of cleaning desired for the wafer W.

The wafers W that pass through at least one of the plurality of chemicalbathes 116-1, through 116-n, the ultra pure water bath 114, and thedrying unit 118 are loaded by the second loading unit 112 onto thecassette C. At this time, cassette C is already on standby at the secondloading unit 112. The loaded cassette C is then transferred by theconveyer to the second counter unit 120 and the unloading unit 122. Asdescribed above, the second counter unit 120 compares the number ofwafers W in the cassette C at this time with the number recorded by thefirst counter unit 104, thereby verifying whether any wafer is missingin the section between the separating unit 108 and the second loadingunit 112.

The structure of the wafer guide 110 according to an exemplary disclosedembodiment of the present invention will now be described in detail withreference to the following drawings.

FIG. 7 shows a front structure of the wafer guide 110 according to anembodiment of the present invention. FIGS. 8 and 9 show a side structureand a perspective structure respectively of the wafer guide 110.

Referring to FIGS. 7 through 9, the wafer guide 110 includes a lowerpanel portion 124; four wafer supporting panel portions 126 a, 126 b,126 c, and 126 d, and four slot portions 128 a, 128 b, 128 c, and 128 d.The four wafer supporting panel portions 126 a, 126 b, 126 c, and 126 dare formed to protrude on the upper end of one side of the lower panelportion 124 and to be perpendicular to the lower panel portion 124.Furthermore, the four wafer supporting panel portions are spacedparallel to each another at a predetermined interval. The four slotportions 128 a, 128 b, 128 c, and 128 d are formed in a saw-tooth shapeto form the upper end of the wafer supporting panel portions 126 a, 126b, 126 c, and 126 d, respectively. The wafer supporting panel portions126 a, 126 b, 126 c, and 126 d, where the slot portions 128 a, 128 b,128 c, and 128 d are formed are made of materials that will minimizedamages to the wafer. These materials include, for example, quartz,coated quartz, peek (polyetheretherketon) and teflon materials.

The wafer supporting panel portions 126 a, 126 b, 126 c, and 126 dinclude a pair of outer wafer supporting panel portions 126 a and 126 b,and a pair of inner wafer supporting panel portions 126 c and 126 d. Theouter wafer supporting panel portions 126 a and 126 b are formed at theright and left side edges of the lower panel portion 124. Furthermore,the pair of inner wafer supporting panel portions 126 c and 126 d areformed between the pair of outer wafer supporting panel portions 126 aand 126 b, and spaced apart from the pair of outer wafer supportingpanel portions at a predetermined interval. This arrangement of outerand inner wafer supporting panels allows the supporting panels to bearranged symmetrically around the center of a wafer.

FIG. 7 illustrates a length 130 and a distance 132. Length 130represents a length of the wafer flat zone of wafer W which is loadedonto the wafer guide 110. Distance 132 represents the distance betweenthe inner wafer supporting panel portions 126 c and 126 d. It ispreferable that the distance 132 be greater than the length 130. This isbecause if the distance 132 is less than the length 130, the amount ofwafer area coming in contact with the slot portions 128 c and 128 d willvary based on the direction of orientation of the wafer flat zone. Forexample, when the wafer W is loaded in the wafer guide 110 such that thewafer flat zone faces the bottom, no scratches occur in the wafer cellarea. However, when the wafer W is loaded in the wafer guide 110 suchthat the wafer flat zone faces the top, a larger area of the wafer W isinserted into the slot portions 128 c and 128 d. Because of a largerarea of the wafer W coming in contact with the slot portions, thepossibility of scratches occurring in the wafer cell area increases.Therefore, in order to minimize the possibility of scratches occurringon the wafer surface when it is mounted in the wafer guide 110regardless of the direction of orientation of the wafer flat zone, it ispreferable to form the inner wafer supporting panel portions 126 c and126 d such that the distance 132 between the inner wafer supportingpanel portions 126 c and 126 d is greater than the length 130 of thewafer flat zone.

The wafer guide 110 may hold the mounted wafer W stably by using thefour wafer supporting panel portions 126 a, 126 b, 126 c, and 126 d. Asthe number of wafer supporting panel portions increases, the wafer maybe held more stably. However, as the number of supporting panel portionsincrease, the contact area between the wafer and the wafer guide 110also increases, thereby increasing the possibility of scratchesoccurring on the wafer cell area. Thus, there is a tradeoff between thestability of support for the mounted wafer and the possibility ofscratches occurring on the wafer surface. In the wafer guide 110, theuse of four wafer supporting panel portions provides sufficient stablesupport for holding the wafer without the wafer supporting panelportions coming in contact with the wafer cell area.

FIG. 7 illustrates the four portions A, B, C, and D of the wafer W thatare in contact with the wafer guide 110. Specifically, the four portionsA, B, C, and D of the wafer W are in contact with the four wafersupporting panel portions 126 a, 126 c, 126 d, and 126 b, respectively.Furthermore, the four supporting panel portions 126 a, 126 c, 126 d, and126 b, support the wafer W by imparting a stabilizing force to portionsA, B, C, and D, respectively. Therefore, the stabilizing force providedby the wafer guide 110 is distributed between the four portions A, B, C,and D of the wafer W. Because the four portions A, B, C, and D of thewafer are firmly supported by the four wafer supporting panel portions126 a, 126 c, 126 d, and 126 b respectively, it is possible to hold thewafer stably in the wafer guide 110 even though the wafer is notinserted deep into the slot portions, as is the practice in the priorart.

The shape of the slot portions formed on the upper end of the waferguide 110 will now be described in detail with reference to FIGS. 10through 13.

FIG. 10 is a partially enlarged side view of the slot portion 128 a or128 b on the outer wafer supporting panel portion 126 a or 126 b of thewafer guide 110. FIG. 11 shows a side view of the slot portion of FIG.10 when a wafer W is held in the slot portion.

Referring to FIG. 10, the slot portion 128 a is formed in a V shape onthe upper end of the outer wafer supporting panel portion 126 a to holdthe wafer W. FIG. 11 depicts two sections of the slot portion 128 a.Specifically, the slot portion 128 a can be divided into an upper slot Eand a lower slot F. The upper slot E is the area which does not come indirect contact with the wafer W when holding the wafer W, and has anopening angle of 30 to 60 degrees. It is preferable to have the openingangle of the upper slot E to be closer to 60 degrees because the upperslot E is not intended to come in direct contact with the wafer W. Thelower slot F is the area which comes in direct contact with the wafer Wwhen holding the wafer W, and has an opening angle 60 to 30 degrees.Because the lower slot F is the area that comes in direct contact withthe wafer W, it is preferable to have the opening angle of the lowerslot F to be closer to 30 degrees. The total length from the upper slotE to the lower slot F is, for example, 8.5 mm. Specifically, the lengthof the upper slot E is 4.3 mm, and the length of the lower slot F is 4.5mm.

When the wafer W is inserted into the slot portion 128 a of the outerwafer supporting panel portion 126 a, the wafer W is inserted into thedeepest end of the lower slot F. The length of the deepest end of thelower slot F may be very small in comparison with the total length ofthe slot portion 128 a. For example, as shown in FIG. 11, the length ofthe deepest end of the lower slot F is 0.57 mm of the total length of8.5 mm of the slot portion 128 a. Because only a small portion of theslot portion 128 a is in direct contact with the wafer W, the amount ofwafer cell area in contact with the slot portion is also small, therebyleading to few or no scratches being formed in the wafer cell area.

FIG. 12 is a partially enlarged view of a slot portion 128 c or 128 d ofthe inner wafer supporting panel portion 126 c or 126 d in the waferguide 110. FIG. 13 shows a side view of the slot portion of FIG. 12 whena wafer W is held in the slot portion.

Referring to FIG. 12, the slot portion 128 c is formed in a Y shape onthe upper end of the inner wafer supporting panel portion 126 c forholding the wafer. As shown in FIG. 13, the slot portion 128 c includesa wide upper slot G and a narrow lower slot H. The wide upper slot G isthe area which does not come in direct contact with the wafer whenholding the wafer, and has an opening angle of 30 to 60 degrees. Becausethe wide upper slot G does not come in contact with the wafer W, it ispreferable to have the opening angle of the wide upper slot G to becloser to 60 degrees. The narrow lower slot H is the area which comes indirect contact with the wafer W and is trench-shaped. The direct contactoccurs because the wafer W is inserted into the narrow lower slot H sothat the wafer W is tightly held in the narrow lower slot H. The totallength from the upper slot G to the lower slot H is, for example, 7.71mm. Specifically, the length of the upper slot G is 4.36 mm and thelength of the lower slot H is 3.5 mm. The width of the lower slot H isgenerally 0.8 mm, but may vary according to the thickness of the waferW.

When a wafer W is inserted into the slot portion 128 c of the innerwafer supporting panel portion 126 c, the wafer is held in the lowerslot H. As shown in FIG. 13, the total depth of the lower slot H is 3.5mm. However, as also shown in FIG. 13, the wafer W is inserted into thelower slot H only up to a depth of 1.75 mm. Thus, only 1.75 mm of thelength of the wafer W is in direct contact with the slot portion 128 c.Generally, 1.75 mm length of the wafer W includes the wafer edge areaonly and does not include any portion of the wafer cell area. Thus, eventhough some scratches may occur within a range of 1.75 mm on the wafersurface (because of the contact with the slot portion,) the scratches donot reach the wafer cell area. Consequently, the scratches do not affectthe production yield of the semiconductor manufacturing process.

FIG. 13 shows the length of the wafer W being inserted into the lowerslot H as being 1.75 mm. However, one skilled in the art will appreciatethat the inserted length shown is exemplary only. The length of thewafer inserted into the lower slot H may depend on the distance betweenthe edge area and the cell area of the wafer and the amount of stabilitydesired in holding the wafer. In the embodiment described and shown inFIG. 13, a wafer may be inserted up to a length of 3.5 mm. Because thedistance between the edge area and the cell area in most currentlyproduced wafers is more than 3.5 mm, an insertion up to a length of 3.5mm may not produce any scratches in the wafer cell area.

The disclosed wafer guide may be used in any system that holds wafersregardless of the orientation of the flat surface of the held wafer.Because the distance between the inner wafer supporting panel portions126 c and 126 d exceeds the length of the wafer flat zone, the depth ofthe wafer inserted into the lower slot H may always be the same,regardless of the orientation of the flat surface of the wafer.Specifically, when a wafer is loaded in the disclosed wafer guide, thewafer is inserted into the slot portion at a depth equal to or less than3.5 mm of the entire wafer area including the wafer flat zone area.Therefore, for wafers whose distance between the wafer edge area and thewafer cell area is greater than 3.5 mm, no scratches may be formed inthe wafer cell area. Therefore there may be no decrease in theproduction yield because of scratches formed on the wafer surface.

As described above, in an exemplary embodiment, the wafer guide includesfour supporting panel portions—a pair of inner supporting panel portionsand a pair of outer supporting panel portions. Because of the use offour supporting panel portions, it may be possible to insert the waferup to a lower depth into the slot portions formed at the upper end ofthe supporting panel portions as compared to an insertion depth in aprior art wafer guide. With the lower insertion depth in the disclosedwafer guide, the contact area between the slot portion and the wafer isreduced compared to a prior art wafer guide. Because of the reduction inthe contact area between the slot portion and the wafer, the possibilityof scratches being formed in the wafer cell area reduces. Therefore, useof the disclosed wafer guide may prevent a chip failure resulting fromthe scratches.

The structure of the disclosed wafer guide has been described inaccordance with an exemplary embodiment of the present invention.However, one skilled in the art will appreciate that various otherembodiments of the wafer guide are also possible without departing fromthe scope of the invention. For example, the wafer guide in thedisclosed embodiment includes four wafer supporting panel portions atone side of the lower panel portion. However, in an alternativeexemplary embodiment, the wafer guide may include any number of wafersupporting panel portions.

Furthermore, the wafer guide in the disclosed embodiment includes a flatshaped lower panel portion. Alternatively, the wafer guide may include alower panel portion that is curve shaped such as, for example, U shapedor V shaped. In addition, in the disclosed embodiment, the wafersupporting panel portions are formed perpendicular to the lower panelportion. However, in an alternative embodiment, the wafer supportingpanel portions may be formed at a different angle with respect to thelower panel portion.

In addition, the wafer supporting panel portions in the disclosed waferguide can be formed of quartz, coated quartz, peek (polyetheretherketon)or teflon materials. However, in an alternative exemplary embodiment,the wafer panel supporting portions can be formed of any other materialcapable of securing a wafer stably while minimizing damage to the wafer.

The invention has been described using preferred exemplary embodiments.However, it is to be understood that the scope of the invention is notlimited to the disclosed embodiments. On the contrary, the scope of theinvention is intended to include various modifications and alternativearrangements within the capabilities of persons skilled in the art usingpresently known or future technologies and equivalents. The scope of thefollowing claims, therefore, should be accorded the broadestinterpretation so as to encompass all such modifications and similararrangements.

1. A wafer guide in a wafer cleaning apparatus, the wafer guidecomprising: a lower panel portion; a plurality of wafer supporting panelportions, the plurality of wafer supporting panel portions beingconfigured to protrude from at least one side of the lower panel portionand support a wafer; and a plurality of slot portions, the plurality ofslot portions being configured to form at upper ends of the plurality ofwafer supporting panel portions and hold the wafer by forming contactwith at least a portion of a wafer edge area without forming contactwith a wafer cell area.
 2. The wafer guide according to claim 1, whereinthe wafer supporting panel portions comprise: a pair of outer wafersupporting panel portions formed at right and left side edges of thelower panel portion; and a pair of inner wafer supporting panelportions, spaced apart from the pair of outer wafer supporting panelportions by a predetermined distance, and formed between the pair ofouter wafer supporting panel portions.
 3. The wafer guide according toclaim 2, wherein the pair of inner wafer supporting panel portions arespaced apart from each other by a distance exceeding a length of a waferflat zone.
 4. The wafer guide according to claim 3, wherein a length ofthe wafer inserted into the slot portion of the outer wafer supportingpanel portion is 0.1 to 0.6 mm from a wafer edge.
 5. The wafer guideaccording to claim 4, wherein the length of the wafer inserted into theslot portion of the outer wafer supporting panel portion is 0.57 mm fromthe wafer edge.
 6. The wafer guide according to claim 3, wherein alength of the wafer inserted into the slot portion of the inner wafersupporting panel portion is less than or equal to 3.5 mm from the waferedge.
 7. The wafer guide according to claim 6, wherein the length of thewafer inserted into the slot portion of the inner wafer supporting panelportion is 1.75 mm from the wafer edge.
 8. A wafer guide in a wafercleaning apparatus, the wafer guide comprising: a lower panel portion; apair of outer wafer supporting panel portions, formed at right and leftside edges of the lower panel portion, supporting a wafer; a pair ofinner wafer supporting panel portions formed between the pair of outerwafer supporting panel portions and spaced apart from each other by adistance exceeding a length of a wafer flat zone, supporting the wafer;and a plurality of slot portions, formed at upper ends of the pair ofouter wafer supporting panel portions and the pair of inner wafersupporting panel portions, holding the wafer by forming contact with atleast a portion of a wafer edge area without forming contact with awafer cell area.
 9. The wafer guide according to claim 8, wherein theslot portion formed at the upper end of the outer wafer supporting panelportion comprises: an outer upper slot which does not form contact withthe wafer when holding the wafer; and an outer lower slot which forms alower area of the outer upper slot and forms contact with the wafer whenholding the wafer.
 10. The wafer guide according to claim 9, wherein theouter upper slot and the outer lower slot have an opening angle within arange of 30 to 60 degrees.
 11. The wafer guide according to claim 10,wherein the opening angle of the outer upper slot is 60 degrees, and theopening angle of the outer lower slot is 30 degrees.
 12. The wafer guideaccording to claim 9, wherein a length of the wafer inserted into theouter lower slot is 0.1 to 0.6 mm from a wafer edge.
 13. The wafer guideaccording to claim 12, wherein the length of the wafer inserted into theouter lower slot is 0.57 mm from the wafer edge.
 14. The wafer guideaccording to claim 8, wherein the slot portion formed at the upper endof the inner wafer supporting panel portion comprises: an inner upperslot which does not form contact with the wafer when holding the wafer;and an inner lower slot which forms the lower area of the inner upperslot and which forms contact when holding the wafer.
 15. The wafer guideaccording to claim 14, wherein an opening angle of the inner upper slotis within a range of 30 to 60 degrees.
 16. The wafer guide according toclaim 15, wherein the opening angle of the inner upper slot is 60degrees.
 17. The wafer guide according to claim 16, wherein the innerlower slot has a vertically long trench shape.
 18. The wafer guideaccording to claim 17, wherein a length of the wafer inserted into theinner lower slot is less than or equal to 3.5 mm from a wafer edge. 19.The wafer guide according to claim 18, wherein the length of the waferinserted into the inner lower slot is 1.75 mm from the wafer edge. 20.The wafer guide according to claim 8, wherein the pair of outer wafersupporting panel portions and the pair of inner wafer supporting panelportions are symmetrical around a wafer center area.